library ieee;
use ieee.std_logic_1164.all;

entity controller is
	port (	Funct, Op	: in std_logic_vector(5 downto 0);
        	AluControl	: out std_logic_vector(2 downto 0);
        	MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump	: out std_logic);
end entity;

architecture controller_arch of controller is
	component aludec
	port (	func		: in std_logic_vector(5 downto 0);
			aluop		: in std_logic_vector(1 downto 0);
        	alucontrol	: out std_logic_vector(2 downto 0));
    end component;
    component maindec
    port (  Op		: in std_logic_vector(5 downto 0);
		AluOp		: out std_logic_vector(1 downto 0);
        MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump	: out std_logic);
    end component;

	signal sth : std_logic_vector(1 downto 0);

	begin
		map1 : maindec port map (Op => Op, AluOp => sth, MemToReg => MemToReg, MemWrite => MemWrite, Branch => Branch, AluSrc => AluSrc, RegDst => RegDst, RegWrite => RegWrite, Jump => Jump);

		map2 : aludec port map (func => Funct, aluop => sth, alucontrol => AluControl);
end architecture;
